Phase-locked loops have traditionally been used to adjust automatically the frequency of oscillators. In digital transmission systems, for example, a phase-locked loop is used to produce a clock signal from an oscillator in the receiver that is synchronous with the frequency of the incoming signal. This clock signal controls the regeneration of the incoming signal by other repeater circuitry.
A perennial problem exists with the use of phase-locked loops in PCM transmission systems. Use of traditional phase comparators in such systems results in a loss of oscillator control due to erroneous phase comparisons made during intervals when the incoming data bits are logical zeros. The oscillator frequency, controlled by the phase comparator, then drifts, resulting in errors in the regenerated data until the oscillator is resynchronized to the incoming data frequency.
An approach to the problem of oscillator drift and the resulting loss of data is to decrease the time required to resynchonize the oscillator. In U.S. Pat. No. 3,351,868 to C. W. Farrow, issued Nov. 7, 1967, an exclusive-OR phase comparator and countdown circuit are utilized to minimize the resynchronization or lock-in time. Similarly, in U.S. Pat. to Rettinger, Jr., No. 3,983,506, issued Sept. 28, 1976, a tristate signal conditioner is employed to reduce lock-in time. The signal conditioner turns off the oscillator a predetermined time after the absence of data is detected. When transmitted data is again detected the oscillator is reset to the nominal data frequency.
This approach, as exemplified in the prior art, is not satisfactory for PCM system applications. In such systems, the data can contain a long series of zeros. Proper regeneration of such data requires a continuous running oscillator synchronized to the data frequency.